This invention relates generally to integrated circuit voltage control circuits and more particularly to circuits which operate to control the application of two voltage supplies, or sources, one of such voltage sources being applied during a normal operating mode and the other being applied during a standby, or partial power-down mode.
As is known in the art, many systems, such as digital computer systems, are required to operate with two voltage sources, one for interfacing to the computer internally (e.g., 5 volts) and one for interfacing to external peripherals (e.g., 12 volts). An example of this would be an interface transceiver integrated circuit which takes signals from the computer and translates them to the higher voltages required by external peripherals. The problem with this is that in order to safely power-down such a device, both sources need to go to zero volts so that no current flows in this mode.
However, computers are now required to operate in a standby, or partial power-down mode where only one source is turned on and consumes little power, while the other source (generally the higher voltage source) is turned off. In traditional dual voltage source circuits, this mode of operation is not supported because if the 5 volt source is left on while the 12 volt source is turned off and allowed to go to 0 volts, significant current could begin to flow from the 5 volt source.
One technique used to provide dual voltages is a charge pump circuit. With such circuit, power from an external, typically 5 volt, source is also used to generate an internal, typically 10 volt, source. During one mode, charge pump is turned off and the internal 10 volt source is shorted internally to the external 5 volt source through an internal switch. However, if an external source is used to provide the higher voltage, say 12 volts, a problem can occur when the 12 volt source is allowed to drop while the 5 volts is still applied. For example, referring to FIGS. 1 and 2, an inverter made up of transistors MP1 and MN1, is a typical device which would be powered off a 5 volt source. However, when a 12 volt source is partially powered down, more particularly, if the 12 volt source is allowed to fall below the 5 volt source, excessive current will flow in an internal parasitic transistor device Q (shown in phantom in FIG. 2). The parasitic device Q is formed by the n-type substrate (i.e., the base of Q), the p-type material tied to the 5 volts (i.e., the emitter of Q), and the grounded p-type or p-well material (i.e., the collector of Q). This parasitic device will turn on when the 12 volt source drops below the 5 volt source by a Vbe allowing significant amounts of current to flow from the 5 volt source to ground.